Encoding and decoding techniques using low-density parity check codes

ABSTRACT

Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No. 13/083,341, filed Apr. 8, 2011, which is incorporated herein by reference in its entirety.

BACKGROUND

Many electrical devices and systems exchange information with each other via transmission media, such as metal conductors, fiber optic cables, and air. An inferior or defective transmission medium may cause errors in such information. Exceeding transmission capability (e.g., transmission rate) of the medium can also induce errors. In some situations, the errors can be corrected. Many conventional techniques use codes to check the validity of information after it is received. Some codes may also assist in correcting the errors. For example, a low-density parity check (LDPC) code can be used for error corrections. In some conventional techniques, however, using an LDPC code may involve complex coding operations or may demand a large number of circuit components to operate. Thus, an LDPC code can be unsuitable for some devices or systems.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of an apparatus including an encoder configured to encode message information with respect to an LDPC code to form codewords, according to an embodiment of the invention.

FIG. 2 shows an example of a parity check matrix H of an LDPC code, according to an embodiment of the invention.

FIG. 3 is a flowchart of a method of encoding information based on a parity check matrix H of an LDPC code, according to an embodiment of the invention.

FIG. 4 shows a block structure of a matrix generated from a parity check matrix H of an LDPC code, according to an embodiment of the invention.

FIG. 5 and FIG. 6 show block structures of matrices generated from the matrix of FIG. 4, according to an embodiment of the invention.

FIG. 7 shows a block diagram of a system including an encoder, according to an embodiment of the invention.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of an apparatus 100 including an encoder 101 configured to encode message information u with respect to an LDPC code to form codewords V_(m), according to an embodiment of the invention. Apparatus 100 can include an information source 110 to provide message information u and a memory area 120 to receive codewords V_(m) from encoder 101. Information source 110 can be provided by devices such as a memory controller or a processor. Memory area 120 can include a memory array to store codewords V_(m). Encoder 101 and memory area 120 can be included in a same device, such as a memory device or a memory controller. Apparatus 100 may include a memory module, a system or device capable of transmitting and receiving information wirelessly, and/or other communication systems and devices having ability to provide error correction in information transmission. FIG. 1 omits additional details of apparatus 100 to focus on the embodiments described herein.

Encoder 101 can be realized in the form of an LDPC encoder that generates codewords V_(m) from message information u with respect to an H-matrix 130. H-matrix 130 can be stored internally in apparatus 100 or external to apparatus 100. H-matrix 130 can include parity check matrix H of a LDPC code. As is understood by those skilled in the art, an H-matrix, such as H-matrix 130, of a code used in transmitting information can be generated (e.g., constructed) using various code constructions, such as a progressive edge-growth LDPC code construction, a Reed Solomon LDPC code construction, LDPC code constructions based on Euclidian geometries, LDPC code constructions based on Vandermondematrix and cyclic permutation blocks, and various other LDPC constructions. An H-matrix, such as H-matrix 130, can be generated by a computer.

FIG. 1 shows codewords V_(m)=[p u] to indicate that codewords V_(m) can be systematic codewords containing a combination of parity information p and message information u. Message information u can include a number of information bits. Parity information p can include a number of parity bits. Codewords V_(m)=[p u] can be defined by H-matrix 130 where message bits of message information u can correspond to a portion of the columns of H-matrix 130 and parity bits of parity information p can correspond to another portion of the columns of H-matrix 130. FIG. 1 shows an example of codewords V_(m)=[p u] where parity information p is located in the first codeword position followed by message information u. The order can be reversed. Message information u can be located in the first codeword position followed by parity information p, such that codewords V_(m)=[u p].

In apparatus 100, since message information u is known, with a given H-matrix of a code, such as H-matrix 130, encoding operations performed by encoder 101 involves generating parity information p based on received message information u and the given H-matrix. Then, encoder 101 can combine received message information u with the generated parity information p to form codewords V_(m)=[p u]. Decoding codewords V_(m) to retrieve the original message information u can be done in a reversed order. For example, encoding processes (e.g., steps) performed during encoding to generate parity information p can be performed on codewords V_(m) in a reversed order to generate decoded information. Then, the same H-matrix used for encoding can be used during decoding to generate the original message information u based on the decoded information. The description herein focuses on encoding to generate codewords V_(m)=[p u] based on received message information u and a given H-matrix of an LDPC code, as described in detail with reference to FIG. 2 through FIG. 7.

FIG. 2 shows an example of a parity check matrix H of an LDPC code. Matrix-H is arranged in rows and columns and has a size (n−k+m)×(n), which corresponds to (n−k+m) rows and n columns. Parameter m corresponds to the number of dependent rows of matrix-H. The rank of a matrix is the number of dependent rows of that matrix. Thus, if matrix-H is a full-rank matrix, parameter m=0. If matrix-H is a rank-deficient (e.g., not a full-rank) matrix, parameter m>0. Parameter n is the number of code bits in a codeword. Parameter k is the number of information bits in a codeword. Thus, in each row (each codeword) of matrix-H, there are n total code bits formed by a combination of k information bits and n−k parity bits.

As shown in FIG. 2, matrix-H is an example of a binary matrix having only zeros (“0”) and ones (“1”) entries. LDPC codes use a parity check matrix H containing mostly zeros and a limited number of ones. For simplicity, FIG. 1 shows only some of the entries of matrix-H. Based on a parity check matrix H, such as matrix-H in FIG. 1, an encoder (e.g., encoder 101 in FIG. 1) described herein can generate parity information associated with message information in order to generate codewords that includes a combination of the parity information and the message information.

FIG. 3 is a flowchart of a method 300 of encoding information based on a parity check matrix H of an LDPC code, according to an embodiment of the invention. The parity check matrix H used in method 300 can include matrix-H of an LDPC code described above with reference to FIG. 1 and FIG. 2.

In FIG. 3, method 300 can include an activity 310 to generate a first matrix (e.g., H_(m)) from the parity check matrix H (e.g., matrix-H in FIG. 1 and FIG. 2). The first matrix can be generated such that it has an upper triangular sub-matrix in the top-left corner of the first matrix. Activity 310 can also include calculating the rank of the parity check matrix H that used to generate the first matrix.

If the total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix H, method 300 can include activity 320 to generate parity information to encode message information based at least in part on the first matrix. Method 300 may stop after performing activity 320.

If the total number of rows of the first upper triangular sub-matrix is less than the rank of the parity check matrix H, method 300 may continue with activity 330 to perform an upper triangularization operation on a second sub-matrix of the first matrix to generate (e.g., form) a second matrix (e.g., H_(m2)). Activity of 340 of method 300 can generate parity information to encode message information based at least in part on the second matrix.

Some or all of activities 310, 320, 330, and 340 of method 300 can be performed by a processor of an electronic unit, such as a computer. For example, activities 310, 320, and 330 can be performed by a computer. Some or all of activities 310, 320, 330, and 340 of method 300 can also be performed by an encoder, such as encoder 101 of FIG. 1. Such encoder can be included in a device, such as a processor, a memory controller, or a memory device. Method 300 may include one or more activities described below reference to FIG. 4 through FIG. 7.

FIG. 4 shows a block structure of a matrix H_(m) generated from a parity check matrix H of an LDPC code, according to an embodiment of the invention. Matrix H_(m) can be generated from a parity check matrix H of an LDPC code, such as matrix-H in FIG. 1 or FIG. 2. An encoder described herein (e.g., encoder 101 in FIG. 1) can receive message information and use matrix H_(m) to generate codewords having parity information and the received message information.

Traditionally, a generator matrix G_(m) is used to encode message information. For example, a matrix H=[I_(n-k)|P] can be generated from a matrix-H, where I_(n-k) is an identity sub-matrix, P is a sub-matrix of the matrix G. Then, a matrix G_(m) can be generated from the matrix G, such that G_(m)=[P^(T)|I_(k)] where P^(T) denotes a transpose of sub-matrix P. The codewords=u*G_(m) can be generated, the symbol “*” in this equation denotes multiplication. Thus, in a traditional encoding, generator matrix G_(m) is used to encode message information. The traditional way, however, can be complex and unsuitable for some systems or devices. For example, a large number of circuit components, e.g., exclusive-OR (XOR) gates, may be needed to process and store information associated with generator matrix G_(m) or both generator matrix G_(m) and matrix-H.

The encoder described herein can generate the codewords directly from matrix H_(m), without generating a matrix such as the traditional generator matrix G_(m). The encoder that generates the codewords based on matrix H_(m) as described herein may be less complex and may have a reduced the number of components, e.g., exclusive-OR gates.

As shown in FIG. 4, matrix H_(m) includes sub-matrices T, A, B, E, C, and D located in various portions of matrix H_(m). For example, sub-matrix T is located in a top-left corner portion of matrix H_(m). Sub-matrix B is located in a top-right corner portion of matrix H_(m). Sub-matrix A is located in a middle portion of matrix H_(m) between sub-matrix T and sub-matrix B. Sub-matrix E is located in a bottom-left corner portion of matrix H_(m) below sub-matrix T. Sub-matrix D is located in a bottom-right corner portion of matrix H_(m). Sub-matrix C is located in a middle portion of matrix H_(m) between sub-matrix E and sub-matrix D and below sub-matrix A. The sizes of these sub-matrices are as follows.

T: (n−k−g)×(n−k−g).

A: (n−k−g)×g.

B: (n−k−g)×k.

C: g×g.

D: g×k.

E: g×(n−k−g).

Matrix H_(m) can be generated by performing a process known as greedy upper triangularization operation. This operation generates an upper triangular matrix, which is sub-matrix T, in the top-left corner of matrix H_(m). This operation involves exchanging only rows, exchanging only columns, or exchanging only rows and columns of the parity check matrix H. No arithmetic operations (e.g., no Gaussian elimination operations) on the rows of the parity check matrix H are performed in this operation.

Sub-matrix T is a square upper triangular matrix having (n−k−g) rows and (n−k−g) columns. Sub-matrix T has all ones in its diagonal entries and all zeros below its diagonal entries. If the number of rows of sub-matrix T is equal to the rank R of parity check matrix H, then parameter g=0 in matrix H_(m), such that (n−k−g)=R where g=0. Also, if g=0, then sub-matrices A is eliminated and become part of sub-matrix B, and sub-matrices E, C, and D are eliminated and become parts of sub-matrix T and sub-matrix B. In this case (n−k=R), matrix H_(m)=[T|B], in which sub-matrix T has a size (n−k=R)×(n−k=R) and sub-matrix B has a size (n−k=R)×k.

When an encoder, such as encoder 101 in FIG. 1, uses matrix H_(m) to generate codewords V_(m)=[p u], where u denotes message information, the parity information (p) can be generated as follows (for g=0). For matrix H_(m), a syndrome of valid codewords V_(m) is an all-zero vector of a size n−k, such that equation H_(m)*V_(m) ^(T)=0 is satisfied. Since H_(m)=[T|B] and V_(m)=[p u], by substituting V_(m) ^(T)=[p u]^(T) into equation H_(m)*V_(m) ^(T)=0, the following equation can be obtained.

${\left\lbrack {T\mspace{14mu} B} \right\rbrack \begin{bmatrix} p \\ u \end{bmatrix}} = 0$

Solving the above equation yields Equation (1) below:

Tp=Bu, thus

p=T ⁻¹ Bu.  (Equation 1)

An encoder, such as encoder 101 of FIG. 1, can be configured to generate parity information p of codewords V_(m). Thus, for a given parity check matrix H of an LDPC code, matrix H_(m) shown in FIG. 4 can be generated. If the total number of rows of sub-matrix T of matrix H_(m) is equal to the rank R of the parity check matrix H, then the encoder can be configured to generate parity information p based on Equation (1). The parity information can be combined with received message information u to generate codewords V_(m)=[p u]. Since an encoder described herein can generate codewords V_(m) based on Equation (1) if the total number of rows of sub-matrix T of matrix H_(m) is equal to the rank R of the parity check matrix H, the encoder may store (e.g., store in a memory) only matrix H_(m) (and not the parity check matrix H) and T⁻¹ for encoding because other values, e.g., B and u, are available from matrix H_(m) and from message information u. During encoding, the encoder may access a memory to retrieve the stored entries of T⁻¹ and matrix H_(m) to generate parity information p based on Equation (1) and generate codewords V_(m)=[p u].

If the total number of rows of sub-matrix T of matrix H_(m) is less than the rank R of the parity check matrix H, additional operations can be performed on matrix H_(m) of FIG. 4 to generate the parity information, as described below with reference to FIG. 5 and FIG. 6.

As described above with reference to FIG. 4, matrix H_(m) can be generated by exchanging only rows or columns, or both, of the parity check matrix H. The process used to generate matrix H_(m) may also include generating (e.g., creating) a tracking record (e.g., a map). This tracking record can track (e.g., map) position numbers of rows or columns of the parity check matrix H that have been exchanged during the generation of matrix H_(m). Since sub-matrix T of matrix H_(m) is generated by exchanging columns of the parity check matrix H, the tracking record also contains a link between a position number of at least one column of the sub-matrix T and a position number of at least one column of the parity check matrix H.

The tracking record can be used during decoding of codewords V_(m) to obtain the original message information u. For example, during decoding, operations such as a deinterleaving operation can be performed. Such operations can exchange the columns of codewords V_(m) based on the tracking record, but in a reversed order, to generate codewords V, which are not in systematic form. A decoder can be used to decode codewords V using the parity check matrix H to generate the original message information u.

During the upper triangularization operation to generate sub-matrix T of matrix H_(m), the columns of the parity check matrix H can be randomly selected to generate the columns of sub-matrix T. This random selection may increase a probability of sub-matrix T having a size R×R, where R is the rank of the parity check matrix H. The total number of rows of sub-matrix T is equal to R when sub-matrix T has a size R×R. If the size of sub-matrix T is R×R, then matrix H_(m) can have a full triangular structure, e.g., H_(m)=[T|B], where parameter g in FIG. 4 is equal to zero (e.g., n−k=R). As described above with reference to FIG. 4, Equation 1 can be used in an encoder in the case where sub-matrix T has a size R×R.

In some case, depending on the value of the entries of the parity check matrix H, the upper triangularization operation may unsuccessfully generate sub-matrix T having a size R×R (e.g., the total number of rows of sub-matrix T is less than R). In such case, matrix H_(m) does not have full triangular structure but it has an approximate triangular structure, as shown in FIG. 4, where parameter g is not zero. In this case, Equation (1) may be inapplicable for generating the parity information. However, additional operations can be performed on matrix H_(m) to generate matrix H_(m1) (FIG. 5) and matrix H_(m2) (FIG. 6). The parity information can be generated based on matrix H_(m2).

FIG. 5 and FIG. 6 show block structures of matrix H_(m1) and H_(m2), respectively, generated from matrix H_(m) of FIG. 4, according to an embodiment of the invention. Codewords V_(m) can be generated using matrix H_(m2) of FIG. 6, as described below after the description of matrix H_(m1) of FIG. 5.

As shown in FIG. 5, matrix H_(m1) has the same block structure as that of matrix H_(m) of FIG. 4. However, the values of entries of sub-matrices E, C_(m1), and D_(m1) of matrix H_(m1) of FIG. 5 are different from those of corresponding sub-matrices E, C, and D of matrix H_(m) of FIG. 4. As shown in FIG. 5, all entries of sub-matrix E are zeros (“0”). Sub-matrices C_(m1) and D_(m1) may be less sparse (more dense) than corresponding sub-matrices C and D of FIG. 4, due to operations performed on sub-matrix E to make all of its entries zeros. Such operations can include arithmetic operations, e.g., Gaussian elimination operations. Since the rows of sub-matrices E, C, and D are parts of the same rows of matrix H_(m), the operations performed on the rows of sub-matrix E of matrix H_(m) also modify the rows of sub-matrices C and D of matrix H_(m). Thus, after all entries of sub-matrix E become zeros, sub-matrices C and D in FIG. 4 become sub-matrices C_(m1) and D_(m1) in FIG. 5.

FIG. 6 shows a block structure of a matrix H_(m2) generated from matrix H_(m1), according to an embodiment of the invention. From matrix H_(m2), calculations can be performed to obtain equations to generate parity information for codewords V_(m). As shown in FIG. 6, matrix H_(m2) has the same block structure as that of matrix H_(m) of FIG. 5. However, matrix H_(m2) can include a number of rows r having all zeros entries. The specific number of rows and columns matrix H_(m1) and the specific sizes of each of sub-matrices of matrix H_(m1) shown in FIG. 6 are only for illustration purposes to help focus on the description herein.

As described above with reference to FIG. 4, an upper triangularization operation can be performed on the parity check matrix H to generate the upper triangular sub-matrix T (as shown in FIG. 6). In FIG. 5 and FIG. 6, an additional upper triangularization operation can be performed on sub-matrix C_(m1) to make the diagonal of sub-matrix C_(m1) to have as many ones (“1”) as possible. The additional upper triangularization operation may not cause all entries in diagonal of sub-matrix C_(m1) to have values of ones. However, the additional upper triangularization operation may cause at least one entry in the diagonal of sub-matrix C_(m1) to have a value of one. For example, as shown in FIG. 6, the additional upper triangularization operation may cause three out of five entries in the diagonal of sub-matrix C_(m1) to have values of ones. Entries x in sub-matrix C_(m1) can be either one or zero. The additional upper triangularization operation may stop when no additional ones can be form in the diagonal of sub-matrix C_(m1), such as in the case shown in FIG. 6. The additional upper triangularization operation may also cause one or more of rows at the bottom of sub-matrix D_(m1) to have values of zeros. The additional upper triangularization operation generates matrix H_(m2). As shown in FIG. 6, matrix H_(m2) has a number of rows r with all entries having zeros. FIG. 6 shows r=2 as an example. The value of r can vary.

These r rows, having entries with all zeros, correspond to dependent rows in the parity check matrix H. Thus, the r rows can be removed from matrix H_(m2). Therefore, after the r rows are removed, matrix H_(m2) can have fewer rows (fewer by r rows) than matrix H_(m1).

The additional upper triangularization operation performed on sub-matrix C_(m1) can include any combination of exchanging rows, exchanging columns, and arithmetic operations (e.g., Gaussian elimination operations). As a comparison, the upper triangularization operation performed on parity check matrix H to generate triangular sub-matrix T (FIG. 4) may include no arithmetic operations (e.g., exchanging only rows and columns).

The additional upper triangularization operation performed on sub-matrix C_(m1) can also modify the rows and columns of sub-matrices A, B, C_(m1), and D_(m1). Thus, after the additional upper triangularization operation, sub-matrices A, B, C_(m1), and D_(m1) of matrix H_(m1) (FIG. 5) become sub-matrices A_(m2), B_(m2), C_(m2), and D_(m2) of matrix H_(m2) of FIG. 6.

When an encoder, such as encoder 101 in FIG. 1, uses matrix H_(m2) to generate codewords V_(m)=[p u], where u denotes message information, parity information p can be generated as follows.

As described above with reference to FIG. 4, FIG. 5, and FIG. 6, matrix H_(m2) is generated from matrix H_(m1), which in turn is generated from matrix H_(m) (FIG. 4). Since matrix H_(m) has an approximate triangular structure (where parameter g is not zero), parity information p of the systematic codeword of V_(m)=[p_(m) u] can be viewed as consisting of two portions: a (n−k−g)-bit long parity portion p₁ and a g-bit long parity portion p₂. Thus, p=[p₁ p₂], therefore V_(m)=[p u]=[p₁ p₂ u].

For matrix H_(m2), a syndrome of valid codewords V_(m) is an all-zero vector of a size n−k, such that equation H_(m2)*V_(m) ^(T)=0 is satisfied. Since V_(m)=[p₁ p₂ u], V_(m) ^(T)=[p₁ p₂ u]^(T). As shown in FIG. 6,

${H_{m\; 2} = \begin{bmatrix} T & A_{m\; 2} & B_{m\; 2} \\ 0 & C_{m\; 2} & D_{m\; 2} \end{bmatrix}},$

by replacing V_(m) ^(T)=[p₁ p₂ u]^(T) into equation H_(m2)*V_(m) ^(T)=0, the following equation can be obtained.

${\begin{bmatrix} T & A_{m\; 2} & B_{m\; 2} \\ 0 & C_{m\; 2} & D_{m\; 2} \end{bmatrix}\begin{bmatrix} p_{1} \\ p_{2} \\ u \end{bmatrix}} = \begin{bmatrix} 0 \\ 0 \end{bmatrix}$

Solving the above equation yields Equation (2) and Equation (3) below.

C_(m2) p₂=D_(m2) u. Thus,

p ₂=(C _(m2) ⁻¹ D _(m2))  (Equation 2)

Tp₁=(A_(m2) p₂+B_(m2) u). Thus,

p₁=T⁻¹(A_(m2) p₂+B_(m2) u). Substituting p₂=(C_(m2) ⁻¹ D_(m2)) from Equation (2) into equation p₁=T⁻¹(A_(m2) p₂+B_(m2) u) yields Equation (3).

p ₁ =T ⁻¹(A(C _(m2) ⁻¹ D _(m2))+B _(m2) u)  (Equation 3)

Based on Equation (2) and Equation (3), an encoder, such as encoder 101 of FIG. 1, can be configured to generate parity information p of codewords V_(m). Thus, for a given parity check matrix H of an LDPC code, matrix H_(m2) shown in FIG. 6 can be generated. Then, based on matrix H_(m2), Equation (2) and Equation (3) can be calculated to generate parity information p₁ and p₂. The encoder can combine parity information p₁ and p₂ with received message information u to generate codewords V_(m)=[p₁ p₂ u].

The process used to generate matrices H_(m1) and H_(m2), as described above, may also include generating (e.g., creating) a tracking record (e.g., a map). This tracking record can track position numbers of rows or columns of the parity check matrix H that have been exchanged during the generation of matrices H_(m1) and H_(m2). For example, this tracking record can track the position numbers of rows or columns of the parity check matrix H that have been exchanged during both the operations to make all entries of sub-matrix E zeros and the triangularization operations performed on sub-matrix matrix C_(m1). This tracking record can also link (e.g., map) position numbers of rows or columns of the parity check matrix H that have been exchanged during the generation of matrices H_(m1) and H_(m2). Thus, this tracking record also contains a link between the position numbers of the columns of matrix H_(m2) and the position numbers of the columns of parity check matrix H.

The combination of the tracking record generated during the generation of matrices H_(m1) and H_(m2) (FIG. 5 and FIG. 6) and the tracking record generated during the generation of matrix H_(m) (FIG. 4) can be used together with the parity check matrix H during decoding of codewords V_(m) to obtain the original message information u. The generation of matrices H_(m), H_(m1), and H_(m2) and associated activities, such as generation of tracking record and Equations 1, 2, and 3, can be performed by an electronic unit, such as a computer. For example, such electronic unit may receive input information associated with parity check matrix H. Then, based on the input information, the electronic unit may generate output information, such as matrices H_(m), H_(m1), and H_(m2), tracking record, and Equations 1, 2, and 3.

As described above, an encoder described herein can generate codewords V_(m) based on Equations (2) and (3). Multiplications in the parameters in Equations (2) and (3) can be obtained by operations such as exclusive-OR additions. Thus, the encoder may store only matrix H_(m2) (and not the parity check matrix H) and the product C_(m2) ⁻¹ D_(m2) because other values, e.g., A, B, and u, are available from matrix H_(m2) and from message information u. Further calculations may provide D_(m)=ET⁻¹ B. Since D_(m) can be available from matrix H_(m1), D_(m2) can also be available and D_(m2) is a modified version of D_(m), D_(m2) is may not need to be stored for encoding operations. Thus, alternatively, the encoder may store (e.g., store in a memory) only matrix H_(m2) and C_(m2) ⁻¹ and T⁻¹ (without storing D_(m2)). During encoding, the encoder may access a memory to retrieve entries of matrix H_(m2) and C_(m2) ⁻¹ and T⁻¹ to generate parity p₁ and p₂ based on Equations (2) and (3) and generate codewords Vm=[p₁ p₂ u].

As a comparison, a traditional encoding may store sub-matrix P of generator matrix G_(m). Sub-matrix P has a size k×(n−k). In the encoding described herein, each of sub-matrices C_(m2) ⁻¹ and D_(m2) and T⁻¹ of a matrix H_(m2) has a size smaller than the size of sub-matrix P.

FIG. 7 shows a block diagram of a system 700 including an encoder 701, according to an embodiment of the invention. Encoder 701 can correspond to encoder 101 of FIG. 1. For example, encoder 701 can be realized in the form of an LDPC encoder that generates codewords V_(m) from message information u with respect to an H-matrix 730. H-matrix 730 can be stored internally in system 700 or external to system 700.

System 700 can be a memory system having memory devices to store information. For example, system 700 can include a device 710, which can include a memory controller, to control a transfer of information to and from a device 720, which can include a memory device.

As shown in FIG. 7, the information transferred to device 720 can include codewords V_(m), which can correspond to codewords V_(m) described above with reference to FIG. 1 through FIG. 6. Device 720 can include memory cells 721. Device 720 can receive codewords V_(m) from device 710 during a write operation and store codewords V_(m) in memory cells 721. Device 720 can also include a read operation to output codewords V_(m) to device 710. Memory cells 721 can include volatile memory cells, non-volatile memory cells, or both. Examples of volatile memory cells include random-access memory (RAM) cells. Examples of non-volatile memory cells include flash memory cells, resistive random-access memory (RRAM) cells, and phase change memory cells, and other types of non-volatile memory cells.

System 700 can store parameters associated with encoding operations in one or both of memory 725 of device 710 and memory cells 721 of device 720. These parameters can include tracking records, such as the tracking records described above with reference to FIG. 4 through FIG. 6. A decoder 702 of device 710 may use the stored parameters and H-matrix 730 to decode codewords V_(m) (received from device 720) to obtain the original message information u.

System 700 can also include a device 740, which can include a processor, such as general purpose processor, or an application specific integrated circuit (ASIC). In an operation, e.g., a write operation of device 720, device 710 may receive message information u at its input, which is coupled to interface 751. Device 710 may generate codewords V_(m) having message information u and provide codewords V_(m) to its output, which is coupled to interface 752. In another operation, e.g., a read operation of device 720, device 710 may receive codewords V_(m) output from device 720 via interface 752, decode codewords V_(m) to obtain message information u, and then send message information u to device 740 via interface 751. Interfaces 751 can include a wired interface or a wireless interface or a combination of both. Interfaces 752 can include a wired interface or a wireless interface or a combination of both. Each of interfaces 751 and 752 can include a bi-directional interface. For example, interface 752 can include bi-directional conductors (e.g., a serial bus or a parallel bus) to transfer codewords V_(m) to and from device 720 on the same bi-directional conductors.

System 700 can also include a storage device 760. A portion of storage device 760 or entire memory 725 can be external to system 700. Storage device 760 can include any form of computer-readable storage medium comprising instructions, which when implemented by one or more processors (e.g., a processor in a computer or in a wireless communication device) or by device 710 or 740, can perform all operations or a part of operations associated with generation of codewords V_(m) described herein. For example, storage device 760 can include instructions to generate matrices, such as matrices H_(m), H_(m1), and H_(m2), to calculate equations, such as Equations (1), (2), and (3), and to generate tracking records (e.g., rows and columns exchange) described above with reference to FIG. 1 through FIG. 6. The processor that performs the instructions stored in storage device 760 can be included in system externally from system 700. For example, such processor can be a part of a computer different from system 700.

Alternatively or in addition to storage device 760, an electronic unit 770 can operate to generate matrices, such as matrices H_(m), H_(m1), and H_(m2), to calculate equations, such as Equations (1), (2), and (3), and to generate tracking records (e.g., rows and columns exchange) described above with reference to FIG. 1 through FIG. 6. For example, electronic unit 770 may receive input information associated with parity check matrix H. Then, based on the input information, electronic unit 770 may generate output information, such as matrices H_(m), H_(m1), and H_(m2), tracking record, and Equations 1, 2, and 3. At least some of the information (e.g., at least some of the information included in matrices H_(m), H_(m1), and H_(m2), Equations (1), (2), and (3), and the tracking records) generated by the electronic unit 770 can be used by encoder 701 to generate codewords V_(m) and used by decoder 702 to decode codewords V_(m).

A portion of system 700 (e.g., devices 710 and 720) or all of system 700 can be included in the same semiconductor chip, in the same integrated circuit package, or in the same circuit board.

The illustrations of apparatus (e.g., apparatus 100) and systems (e.g., system 700) are intended to provide a general understanding of the structure of various embodiments and are not intended to provide a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein.

Any of the components described above with reference to FIG. 1 through FIG. 7 can be implemented in a number of ways, including simulation via software. Thus, apparatus (e.g., apparatus 100) and systems (e.g., system 700) described above may all be characterized as “modules” (or “module”) herein. Such modules may include hardware circuitry, single and/or multi-processor circuits, memory circuits, software program modules and objects and/or firmware, and combinations thereof, as desired by the architect of the apparatus (e.g., apparatus 100) and as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and ranges simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate or simulate the operation of various potential embodiments.

The apparatus and systems of various embodiments may include or be included in electronic circuitry used in high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

The embodiments described above with reference to FIG. 1 through FIG. 7 include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed in a second sub-matrix in a second portion of the first matrix to form a second matrix. Parity information to encode the message information can be generated based on the second matrix. The encoding described herein can combine the parity information and the message information to form codewords. Decoding of the codewords can also be performed. For example, processes (e.g., steps) performed during encoding to generate the parity information can be performed in a reversed order to generate decoded information. Then, the same H-matrix used for encoding can be used during decoding to generate the original message information. Other embodiments including additional apparatus and methods are described.

The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. 

What is claimed is:
 1. An apparatus comprising: an input to receive message information; an encoder to generate codewords having the message information and parity information, and to generate the parity information based on an equation calculated from a combination of at least an inverse of a triangular sub-matrix generated from a first portion of a parity check matrix of a low-density parity check code and a sub-matrix generated from a second portion of the parity check matrix; and an output to provide the codewords.
 2. The apparatus of claim 1, wherein the equation includes p=T⁻¹(Bu), wherein p denotes the parity information, T⁻¹ denotes the inverse of the triangular sub-matrix, B denotes the sub-matrix generated from the second portion of the parity check matrix, and u denotes the message information.
 3. The apparatus of claim 1, wherein the encoder is configured to store entries of the inverse of the triangular sub-matrix.
 4. The apparatus of claim 1, wherein the encoder is included in a memory device coupled to receive the codewords, the memory device including memory cells to store the codewords.
 5. The apparatus of claim 4, wherein the memory device is configured to output the codewords in a read operation of the memory device.
 6. The apparatus of claim 5, wherein the input and the output comprise a bi-directional interface of the memory device.
 7. The apparatus of claim 1, wherein the apparatus is configured to store a record linking a position number of at least one column of the triangular sub-matrix with a position number of at least one column of the parity check matrix.
 8. An apparatus comprising: an input to receive message information; and a module to generate codewords having the message information and parity information, the module configured to generate a portion of the parity information based on a first equation calculated from at least an inverse of a first sub-matrix in a first portion of a matrix, the first sub-matrix including a diagonal entry having a value of one, the module also configured to generate an additional portion of the parity information based on a second equation calculated from at least a triangular sub-matrix in a second portion of the matrix; and an output to provide the codewords.
 9. The apparatus of claim 8, wherein the first equation includes p₂=(C_(m2) ⁻¹ D_(m2))u, the second equation includes p₁=T⁻¹ (A_(m2) p₂+B_(m2) u), wherein p₁ and P₂ denote the portions of the parity information, C_(m2) denotes the first sub-matrix in the first portion of a matrix, T⁻¹ denotes an inverse of the triangular sub-matrix, and A_(m2), B_(m2), and D_(m2) denote other sub-matrices of the matrix, the matrix having a block structure $\begin{bmatrix} T & A_{m\; 2} & B_{m\; 2} \\ 0 & C_{m\; 2} & D_{m\; 2} \end{bmatrix}.$
 10. The apparatus of claim 8, wherein the module is configured to store entries of the inverse of the triangular sub-matrix, and entries of the inverse of the first sub-matrix in the first portion of a matrix.
 11. The apparatus of claim 8, wherein the module is configured to store entries of a parity check matrix of a low-density parity check code, and wherein the matrix is generated from the parity check matrix.
 12. The apparatus of claim 11, wherein the module is configured to store a record linking at least a portion of column numbers of the matrix with at least a portion of column numbers the parity check matrix.
 13. The apparatus of claim 8, wherein the module comprises a memory device having memory cells to store the codewords.
 14. A method comprising: receiving message information; generating parity information based on an equation calculated from at least an inverse of a triangular sub-matrix and a second sub-matrix, the triangular sub-matrix generated from a first portion of a parity check matrix of a low-density parity check code, the second sub-matrix generated from a second portion of the parity check matrix; and generating a codeword based at least in part on the parity information.
 15. The method of claim 14, wherein the equation includes p=T⁻¹(Bu), wherein p denotes the parity information, T⁻¹ denotes the inverse of the triangular sub-matrix, B denotes the second sub-matrix, and u denotes the message information.
 16. The method of claim 14, further comprising: accessing a memory to retrieve entries of the inverse of the triangular sub-matrix.
 17. The method of claim 14, wherein the codewords include a combination of the message information and the parity information.
 18. The method of claim 14, further comprising: decoding the codeword to retrieve the message information.
 19. The method of claim 14, further comprising: generating an additional portion of the parity information based on a second equation calculated from at least a triangular sub-matrix in a second portion of the matrix.
 20. The method claim 19, wherein the first equation includes p₂=(C_(m2) D_(m2))u, the second equation includes p₁=T⁻¹(A_(m2) p₂+B_(m2) u), wherein p₁ and p₂ denote the portion and the additional portion of the parity information, C_(m2) denotes the first sub-matrix, T denotes the triangular sub-matrix, and A_(m2), B_(m2), and D_(m2) denote other sub-matrices of the matrix, the matrix having a block structure $\begin{bmatrix} T & A_{m\; 2} & B_{m\; 2} \\ 0 & C_{m\; 2} & D_{m\; 2} \end{bmatrix}.$ 